Date: February 21-23, 2012
Location: San Jose, CA
Daniel Gitlin, Tabula's Vice President of Manufacturing Technology, and a veteran in PLD advanced process technology, will discuss Tabula's approach to overcoming the limitations FPGA technologies have reached in supporting the explosive growth of bandwidth. The Summit will take place at the Doubletree hotel in San Jose, California. Mr. Gitlin will participate in the Ethernet Chipsets session (1-103), an executive panel discussion focusing on the latest advances in Ethernet technology, particularly in 40/100 GbE. The session starts at 3:10pm on Wednesday, February 22nd.
> For more information
Date: February 27 - March 2, 2012
Location: Monterey, CA
FPGAs in 2032: Challenges and Opportunities in the next 20 years
Chair: Vaughn Betz, University of Toronto
Chair: Lesley Shannon, Simon Fraser University
Abstract: This year marks the 20th anniversary of the FPGA
Symposium, so itis fitting that this workshop will look forward to the
changes that the next 20 years are likely to bring to programmable
systems. A panel of visionaries from industry and academia will
present their thoughts on major research areas, challenges and
opportunities that will emerge over the coming two decades. Questions
abound, from what the software flow in 2032 will be, to what
architectures will suit chips with 100 billion transistors, and what the
fabrication technology will be.
Steve Teig, Tabula's Founder and CTO, and a veteran in the EDA industry will discuss his predictions for "PLDs in 2032".
The session starts at 2:00pm on Wednesday, February 22nd.
Presenters:
Mr. Bob Blainey, IBM Fellow, Compiler and Next-Generation System Software
Dr. Ivo Bolsens, CTO and Senior Vice-President of Xilinx
Dr. Misha Burich, CTO and Senior Vice-President of R & D of Altera
Professor Peter Cheung, Head of the Department of Electrical Engineering, Imperial College London
Dr. Michael Flynn, Chairman of Maxeler Technologies and
Professor Emeritus at Stanford University
Mr. Shep Siegel, Founder and CTO of Atomic Rules
Mr. Steve Teig, President and CTO of Tabula
> For more information
Date: April 10, 2012
Location: San Jose, CA
Rise and Fall of New Fabless Startups => New Model for IP/ASSP Collaboration
By Marc Miller, Sr. Director of Marketing, Tabula
The Largest and Most Focused Event Dealing with Silicon IP in Santa Clara!
For the 3nd Time in Santa Clara - Largest and Most Focused Event for the Silicon IP Sector!
Uniquely tailored for Silicon IP Professionals, Design Professionals.
Come and meet the Who's Who in the Silicon IP space
Biography:
Marc Miller is Sr. Director of Marketing at Tabula where he creates new business models, product categories, and product definitions. Previously at Altera he led Stratix GX product definition and drove its transceiver PHY hard IP acquisition that has provided the cornerstone for multiple generations of that product line. At LSI Logic Marc led the transceiver team than implemented their first Gigabit CMOS SerDes and ran the Computer Strategic Business Unit. Marc started his career in microprocessor design at Digital.
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Date: May 8-9, 2012
Location: San Jose, CA
9:45 Part I - Case Studies: Success Stories in Funding and M&As
Dennis Segers, Tabula's CEO, and a 35 year veteran of the semiconductor industry will participate in an executive panel discussing Success Stories in Funding and M&As.
Abstract:
With the typical funding requirements to get a fabless semi company to exit now taking $50-250 million, semiconductor startups are finding it extremely challenging to generate the necessary financing to develop their initial products and grow their business to compete on a global scale. This is made even more difficult now that the time to do this is approaching the 10-year life of traditional VC funds and it is increasingly hard to achieve an exit in line with investors' expected return on investments. In today's environment, what are some of the challenges experienced and what does it take to lead a company from initial funding to the successful completion of an exit strategy?
Moderator: David Baillie, Chief Executive Officer, CamSemi
Panelists:
Stan Boland, Former CEO and co-founder of Icera Inc.; Senior Vice President, Mobile Business Unit, NVIDIA Corporation
Dennis Segers, Chief Executive Officer, Tabula
Marc Steifman, Managing Director, Head of Technology Investment Banking, Piper Jaffray & Co
> For more information
Date: December 7, 2011
Location: Grenoble, France
Marc Miller, Sr. Director of Marketing
"Rise and Fall of New Fabless Startups -> New Model for IP/ASSP Collaboration"
> For more information
Date: June 6, 2011 at 3:00pm
Location: San Diego, California
IP SoC Village Presentation
Marc Miller, Sr. Director of Marketing
"ASAP TM Program - A New Platform for ASSPs"
Embedded Theatre
Exhibit Hall F - Booth #1825
San Diego Convention Center, CA
> For more information
Date: Nov 18, 2010
Keynote:
"A new computing paradigm for the 21st century" by Steve Teig, Founder, President and CTO of Tabula
Abstract:
Today's System-on-Chip (SoC) devices involve multiple processors and multiple hardware accelerators in closely-coupled or networked topologies. In addition to tiered memory structures and multi-layer bus structures, these systems - which may be executing hundreds of millions to tens of billions of instructions per second - feature extremely complex software components, and this software content is currently increasing almost exponentially.
The "von Neumann architecture" for computers, which was popularized by the Hungarian American mathematician John von Neumann, has now dominated computing for more than 65 years. It is a masterpiece of simplicity: readily implemented in hardware, easily understood by software developers, and amenable to compilation from a wide variety of programming languages. Unfortunately, it achieves its simplicity from the fundamental, non-physical assumption that reading from a memory location takes negligible, constant time independent of the size of the memory.
Decades of innovation in computer architecture and compiler design for uniprocessors has masked some of the von Neumann computer's intrinsic latency. The power requirements for this disguise have become prohibitive, though, which has ended the long, exponential rise in uniprocessor clock frequency. Multi-core processors, the semiconductor industry's response, have the virtue that they can clearly be built, but no one knows how to program them! Further, they make the same negligible-latency assumptions as uniprocessors, but disguising that latency is now quadratically more difficult.
In his keynote presentation, Steve Teig will show that highly useful yet non-physical oversimplifications such as the von Neumann architecture have numerous historical precedents from which we can learn. These examples suggest that a more physically aware, non-von Neumann machine could offer significantly higher-performance and far more power-efficient computation. Steve will also present some thoughts on what such a machine might look like - hint: it is not an array of microprocessors! - and how one might program it. It is only by simultaneously approaching architecture, hardware, and software - seeing them as aspects of a cohesive whole as von Neumann did - that we can maximize our chances of going beyond von Neumann computing.
> For more information
Date: Dec 1, 2010
Location: Gent, Belgium
Symposium "A new era for high-level synthesis"
"Spacetime: a programmable fabric beyond the FPGA" by Steve Teig, Founder, President and CTO of Tabula
Abstract:
Programmable fabrics, such as FPGAs, have existed since at least 1984, but commercial FPGA architectures have stagnated over the last decade, leaving today's FPGAs with the same 20-50x price/performance disadvantage vs. ASICs that they had 10 years ago. Spacetime is a new approach to constructing a programmable fabric, based on novel, ultra-high-performance, sub-ns-reconfigurable hardware coupled with an easily grasped metaphor that completely hides the underlying, on-the-fly reconfiguration, thus facilitating the automated mapping of computations to the fabric. While the idea of reconfiguration is not new, dating back to Turing or even earlier, the representation of the temporal aspects of computing in a spatial way, as Special Relativity does for physics, is new, and Minkowski's space-time geometry concisely encapsulates key requirements for the correctness and performance of computations mapped to MIMD fabrics, such as FPGAs, multi-core microprocessors, and Tabula's 3PLDs. As such, our embodiment of these ideas in Spacetime offers not only a 5x price/performance advantage vs. FPGA but also vital aspects of the compiler technology that will be required for multi-core and other multi-computing hardware implementations.
> For more information
Date: Tuesday, June 15, 2010 Time: 12:00 PM - 2:00 PM
Location: Anaheim, CA Location: 303AB
"Beyond von Neumann Computing" by Steve Teig, Founder, President and CTO of Tabula
Steve Teig, president and chief technology officer (CTO) of Tabula, will describe an approach to move beyond von Neumann computing during a luncheon hosted by the IEEE Council on Electronic Design Automation (CEDA) at the 47th Design Automation Conference (DAC).
The lunch, open to all DAC attendees on a first-come, first-served basis, will be held Tuesday, June 15, from noon-2 p.m. in Room #303 at the Anaheim Convention Center in Anaheim, Calif.
In his talk, Teig, inventor of Tabula's Spacetime 3-Dimensional Programmable Logic Architecture, will describe a simultaneous approach to design of architecture, hardware and software. He will explain how he sees them as aspects of a cohesive whole, similar to the way John von Neumann, inventor of the von Neumann architecture, and Alan Turing, developer of the Turing machine, did. Teig will illustrate why he believes that a new approach to architectural design will maximize the opportunities to go beyond von Neumann computing.
Register today to meet with the Tabula Sales and Marketing team at DAC.
Booth #294 at the TSMC Open Innovation Forum, Analog Bits
> For more information, event press release
Date: April 10, 2010
Location: San Jose, California
Tabula to demo SerDes at the TSMC symposium in our partner Analog Bits booth #14 and #15
> For more information
Date: March 29-31, 2010
Location: Santa Clara, CA, Santa Clara Convention Center
Using StarRC OpenAccess Interface for Accurate and Productive Custom IC Design Paper Presentation
by Mahesh Kondajji Sr. Staff Engineer CAD at Tabula
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