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To meet the increasing complexity of today's electronic systems, the integration of programmable logic devices and development tools must be completely seamless, enable increasingly better price/performance, and provide designers with a familiar design environment supporting industry standard design languages, constraints specifications and scripting. In support of Tabula's Spacetime™ architecture and ABAX™ family of 3PLD devices, Tabula introduces the Stylus™ software cloud computing design platform. Designers can now harness computing power through the web from cloud resources to take full advantage of Tabula's breakthrough Spacetime 3D architecture, accelerating end-product time-to-market at lower costs. The industry's first integrated synthesis and place-and-route (SP&R) package
supporting 3PLD devices, Stylus manages the underlying reconfiguration transparently, automatically mapping standard RTL into Spacetime. In addition, it combines leading-edge synthesis technology with 3D timing-driven place-and-route within a flow and methodology which are familiar to FPGA and ASIC designers, thus requiring little or no learning curve.
Stylus Cloud Computing Software Brochure >
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DESIGN ANALYSIS CAPABILITIES
To enhance designers' productivity, Stylus makes it possible to view and create pin constraints, floor-plans, design schematics, timing reports, and constraint files, all within
a single and intuitive GUI.
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MACRO/ SOFT IP DESIGN LIBRARY
The design library macros are optimized for area and performance. They deliver use models that abstract away the details of the Spacetime operation. The macros are fully integrated into the Stylus design flow, and in most cases are infered directly from RTL by Stylus, or can be instantiated in the user RTL. Fully parameterized memory macros generate user-memories of arbitrary width and depth, with up to 16 ports. All ABAX RAM features are supported, including dual and single clock RAM, asynchronous and fully asymmetric FIFO, and register files. Parallel I/O macros deliver complex programmability to users in the form of pre-verified use models for direct instantiation in their designs. Source and system synchronous interfaces, combinatorial I/O, registered I/O, and multi-data rate I/O are all supported. Clocked and strobed data recovery, as well as static and dynamic per-bit deskew are available. Serial I/O macros deliver preconfigured support with parameterization for all common protocol use models. The full flexibility of the Tabula SerDes is delivered for standard and custom protocols. THIRD-PARTY SOFT IP
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