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To meet the increasing complexity of today's electronic systems, the integration of programmable logic devices and development tools must be completely seamless, enable increasingly better price/performance, and provide designers with a familiar design environment supporting industry standard design languages, constraints specifications and scripting. In support of Tabula's Spacetime™ architecture and ABAX™ family of 3PLD devices, Tabula introduces the Stylus™ software cloud computing design platform. Designers can now harness computing power through the web from cloud resources to take full advantage of Tabula's breakthrough Spacetime 3D architecture, accelerating end-product time-to-market at lower costs. The industry's first integrated synthesis and place-and-route (SP&R) package supporting 3PLD devices, Stylus manages the underlying reconfiguration transparently, automatically mapping standard RTL into Spacetime. In addition, it combines leading-edge synthesis technology with 3D timing-driven place-and-route within a flow and methodology which are familiar to FPGA and ASIC designers, thus requiring little or no learning curve.

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DESIGN FLOW

Stylus design flow works with your existing design methodology. There is no need to change or adapt your design environment to accommodate Spacetime's 3D nature, and virtually no learning curve
Stylus automatically maps, places, and routes standard RTL to the ABAX device
- No knowledge of Spacetime operation is required to implement a design
- User feedback and reporting are provided in the context of the RTL input
- Fabric and I/O timing information are extracted from standard SDC timing constraints
All control of the hardware reconfiguration is automatically and transparently managed by Stylus

USER INTERFACE CAPABILITIES

INPUTS AND OPTIONS
Integrated design project flow Managed within a common user interface GUI and batch execution Job execution automatically targets compute cluster Intelligent reruns: only the phases whose inputs have changed are run Common interface for all user activities Setting up designs for processing Running designs and monitoring their progress Examining results and analyzing design data Flow Project Management Specifying input files Examining inputs (including all HDL source files) Controlling options for each phase Visually inspecting log files (including smart table format) Starting and stopping runs Exporting bit streams to ABAX parts Interface tuned for high usability Modern interface with intuitive and simple controls Simple tabbed interface for managing multiple views Tear off tabs for use on multiple monitors Visually inspecting log files (including smart table format) Pervasive support for undo Support for hardware accelerated graphics for place-and-route

INPUTS AND OPTIONS

Integrated design project flow
- Managed within a common user interface
- GUI and batch execution
- Job execution automatically targets compute cluster
- Intelligent reruns: only the phases whose inputs have changed are run

Common interface for all user activities
- Setting up designs for processing
- Running designs and monitoring their progress
- Examining results and analyzing design data

Flow Project Management
- Specifying input files
- Examining inputs (including all HDL source files)
- Controlling options for each phase
- Visually inspecting log files (including smart table format)
- Starting and stopping runs
- Exporting bit streams to ABAX parts

Interface tuned for high usability
- Modern interface with intuitive and simple controls
- Simple tabbed interface for managing multiple views
- Tear off tabs for use on multiple monitors
- Visually inspecting log files (including smart table format)
- Pervasive support for undo
- Support for hardware accelerated graphics for place-and-route

HIGH AND LOW LEVEL CONTROLS
Flows are controlled by projects Individual phases can be controlled via Tcl commands and options