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TSE FAMILY OVERVIEW

3D Programmable Logic Devices ABAX 3PLD Development Kit Intellectual Property Documentation Standard Products I-100 100Gb Ethernet Solution I-40 40Gb Ethernet Solution TSE100x1 Packet Search Engine NetASAP Datacenter Solutions ASAP PARTNER PROGRAM





SALES REPRESENTATIVES

INDUSTRY OVERVIEW


COMPANY FAST FACTS:
Founded: 2003
Founded by EDA pioneer, Steve Teig
100+ employees
120+ patents granted

CORPORATE HEADQUARTERS:
3250 Olcott St.
Santa Clara, CA 95054
Phone: (408) 986-9140
Fax: (408) 986-9146

ANALYST, PRESS INQUIRES:
Sabrina Joseph, Managing Partner
Morphoses
560 S. Winchester Blvd., Suite 500
San Jose, CA 95128
Tel: (408)236-7373
tabulapr@morphoses.com

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Tabula Ternary Search Engines (TSEs) smooth your transition from IPv4 to IPv6 while giving you the opportunity to differentiate your platform. These TSEs take a new approach to performing ternary searches for improved security, QoS, bandwidth and latency. They are virtualization optimized with up to 8 distinct tables for associative look-ups boosting security in the network and the data center. The 1M exact entries provide benefits such as huge MAC-to-MAC tables covering all servers in a data center.

Ternary Search Engines rapidly match headers and payloads to multiple values selected by masks to fields of interest. Packet header fields include protocol, source and destination IP address, and port numbers. ASAP TSEs match N-tuple fields with total lengths that typically vary between 40 to 640 bits of width. An example of fields matched are shown below.

TSE100x1 Brochure >

For more information on our TSE100x1 device   To purchase a TSE100x1 device

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FIELDS MATCHED
  • Source IPv4/IPv6 address (32 to 128 bits)
  • Destination IPv4/IPv6 address (32 to 128 bits)
  • Source port (16 bits)
  • Destination port (16 bits)
  • Protocol (8 bits)
  • Board ID (10 bits)
  • Interface ID (8 bits)
  • VLAN ID (12 bits)
  • User defined fields

TSE100


Existing search engines function by performing power-intensive, brute-force associative matches of value and mask pairs.
Tabula TSEs combine features of an algorithmic exact-match circuit along with a novel associative search circuit that is optimized to run on Tabula's Spacetime architecture. Tabula's Spacetime architecture offers a unique competitive advantage for Ternary Search Engines by enabling 16 independent accesses to over 500 memories per cycle.

KEY FEATURES
  • Mask and value widths of: 640, 320, 160, 80 and 40 bits
  • Search rates of up to 100 MSPS
  • Large exact match tables, up to 1,048,576 exact match entries using off-chip DDR Memory
  • Virtualization Optimized: Up to 8 tables supporting up to 16K fully associative match entries using on-chip 16-Port RAM
  • Priority encoding returns highest priority match
  • Power optimized to reduce memory accesses as compared to non-algorithmic TCAM
  • Interlaken Look-Aside or PCI Express or standard parallel interfaces

TSE100x1 BLOCK DIAGRAM

The devices utilizes on-chip 8-Port RAMs and on-chip 16-Port RAMs to implement the associative and exact match storage entries. Optional off-chip DDR DRAM can be used to expand the number of exact-match entries. The TSE product family offers Interlaken Look-Aside or PCI Express or standard parallel interfaces. TSE100 Block Diagram